Verilog Interview Questions

1. What is the difference between Behavior modeling and RTL modeling?
2. What is the benefit of using Behavior modeling style over RTL modeling?
3. What is the difference between blocking assignments and non-blocking assignments ?
4. How do you implement the bi-directional ports in Verilog HDL
5. How to model inertial and transport delay using Verilog?
6. How to synchronize control signals and data between two different clock domains?
7. Create 4 bit multiplier using a ROM and what will be the size of the ROM. How can you realize it when the outputs are specified.
8. How can you swap 2 integers a and b, without using a 3rd variable
9. Which one is preferred? 1's complement or 2's complement and why?
10. Which one is preferred in FSM design? Mealy or Moore? Why?
11. Which one is preferred in design entry? RTL coding or Schematic? Why?
12. Design a 2 input OR gate using a 2:1 mux.
13. Design a 2 input AND gate using a 2 input XOR gate.
14. Design a hardware to implement following equations without using multipliers or dividers.
a. out = 7x + 8y;
b. out = .78x + .17y;
15. Design Gray counter to count 6.
16. Design XOR gate using just NAND gates.
17. Create "AND" gate using a 2:1 multiplexer. (Create all other gates too.)
18. How are blocking and non-blocking statements executed?
19. How do you model a synchronous and asynchronous reset in Verilog?
20. What happens if there is connecting wires width mismatch?
21. What are different options that can be used with $display statement in Verilog?
22. Give the precedence order of the operators in Verilog.
23. Should we include all the inputs of a combinational circuit in the sensitivity list? Give reason.
24. Give 10 commonly used Verilog keywords.
25. Is it possible to optimize a Verilog code such that we can achieve low power design?
26. Which is updated first: signal or variable?