VHDL Interview Questions

What is the difference between using direct instntiations and component ones except that you need to declare the component ?

What is the use of BLOCKS ?

What is the use of PROCEDURES?

What is the usage of using more then one architecture in an entity?

What is a D-latch? Write the VHDL Code for it?

Implement D flip-flop with a couple of latches? Write a VHDL Code for a D flip-flop?

Differences between Signals and Variables in VHDL? If the same code is written using Signals and Variables what does it synthesize to?

Differences between functions and Procedures in VHDL?

Explain the concept of a Clock Divider Circuit? Write a VHDL code for the same?

What you would use in RTL a 'boolean' type or a 'std_logic' type and why.

What are/may be the implications of using an 'integer' type in RTL.

A timing path fails: what are your options?

What are VHDL structures, give an example to exploit them

What is grey coding, any example where they are used

Discuss Async interfaces

Metastability

Synopsys unwanted latch

Verilog blocking vs non-blocking

VHDL variables: example where you have to use them

What is pipelining and how it may improve the performance

What are multicycle paths.

What are false paths

What are Async counters, what are advantages of using these over sync counters. and what are the disadvantages

Sensitivity List:
How does it matter.What will happen
if you dont include a signal in the sensitivity list
and use/read it inside the process

How you will implement a C language pointer in VHDL

What is Design For Test and why it is done.

What is clock gating? How and why it is done.
Low Power: discuss how it may be done

Discuss disadvantages/challenges of shrinking technology

What is pipelining, how may it affect the performance of a design
What is the difference between transport delays and inertial delays in VHDL
What determines the max frequency a digital design may work on
Why thold(hold time) is not included in the calculation for the above.
What will happen if output of an inverter is shorted to its input
What is noise margin.
Why are p-mos larger than n-mos in CMOS design.
Draw DC curve of inverter and Re-Draw it if pmos and nmos are equal.
What is Latch-up
How can an Inverter work as an amplifier
Design a state machine which divides the input frequency of a clock by 3.

Why does a pass gate requires two transistors(1 N and 1 P type) Can we use a
single transistor N or P type in a pass gate? If not why? and if yes then in what conditions?

Why CMOS why not N-MOS or P-MOS logic, when we know that the number
of gates required in CMOS are grater than in n-mos or p-mos logic.

How much is the max fan out of a typical CMOS gate. Or alternatively,

discuss the limiting factors.

What are dynamic logic gates? What are their advantages over conventional logic gates

Design a digital circuit to delay the negative edge of the input signal by 2 clock cycles

What is the relation between binary encoding and grey(or gray) encoding.

Write a vhdl function to implement a length independent grey code counter.
alternatively, discuss the logic to do that.

How you will constraint a combinational logic path through your design
in dc_shell.

Make a T Flip Flop using a D Flip Flop

How you will make a Nand Gate function like an inverter.

Design a state machine to detect a '1101' pattern in a stream.
Detect both, overlapping and non overlapping patterns.

What are MISRs, example usage?