FPGA Interview Questions

1) What is minimum and maximum frequency of dcm in spartan-3 series fpga?

Spartan series dcm’s have a minimum frequency of 24 MHZ and a maximum of 248

2)Tell me some of constraints you used and their purpose during your design?

There are lot of constraints and will vary for tool to tool ,I am listing some of Xilinx constraints
a) Translate on and Translate off: the Verilog code between Translate on and Translate off is ignored for synthesis.
b) CLOCK_SIGNAL: is a synthesis constraint. In the case where a clock signal goes through combinatorial logic before being connected to the clock input of a flip-flop, XST cannot identify what input pin or internal net is the real clock signal. This constraint allows you to define the clock net.
c) XOR_COLLAPSE: is synthesis constraint. It controls whether cascaded XORs should be collapsed into a single XOR.
For more constraints detailed description refer to constraint guide.

3) Suppose for a piece of code equivalent gate count is 600 and for another code equivalent gate count is 50,000 will the size of bitmap change?in other words will size of bitmap change it gate count change?

The size of bitmap is irrespective of resource utilization, it is always the same,for Spartan xc3s5000 it is 1.56MB and will never change.

4) What are different types of FPGA programming modes?what are you currently using ?how to change from one to another?

Before powering on the FPGA, configuration data is stored externally in a PROM or some other nonvolatile medium either on or off the board. After applying power, the configuration data is written to the FPGA using any of five different modes: Master Parallel, Slave Parallel, Master Serial, Slave Serial, and Boundary Scan (JTAG). The Master and Slave Parallel modes
Mode selecting pins can be set to select the mode, refer data sheet for further details.

5) Tell me some of features of FPGA you are currently using?

I am taking example of xc3s5000 to answering the question .

Very low cost, high-performance logic solution for
high-volume, consumer-oriented applications
- Densities as high as 74,880 logic cells
- Up to 784 I/O pins
- 622 Mb/s data transfer rate per I/O
- 18 single-ended signal standards
- 6 differential I/O standards including LVDS, RSDS
- Termination by Digitally Controlled Impedance
- Signal swing ranging from 1.14V to 3.45V
- Double Data Rate (DDR) support
• Logic resources
- Abundant logic cells with shift register capability
- Wide multiplexers
- Fast look-ahead carry logic
- Dedicated 18 x 18 multipliers
- Up to 1,872 Kbits of total block RAM
- Up to 520 Kbits of total distributed RAM
• Digital Clock Manager (up to four DCMs)
- Clock skew elimination
• Eight global clock lines and abundant routing

6) What is gate count of your project?

Well mine was 3.2 million, I don’t know yours.!

7) Can you list out some of synthesizable and non synthesizable constructs?

not synthesizable->>>>
initial
ignored for synthesis.
delays
ignored for synthesis.
events
not supported.
real
Real data type not supported.
time
Time data type not supported.
force and release
Force and release of data types not supported.
fork join
Use nonblocking assignments to get same effect.
user defined primitives
Only gate level primitives are supported.

synthesizable constructs->>
assign,for loop,Gate Level Primitives,repeat with constant value...

8)Can you explain what struck at zero means?

These stuck-at problems will appear in ASIC. Some times, the nodes will permanently tie to 1 or 0 because of some fault. To avoid that, we need to provide testability in RTL. If it is permanently 1 it is called stuck-at-1 If it is permanently 0 it is called stuck-at-0.

9) Can you draw general structure of fpga?

10) Difference between FPGA and CPLD?

FPGA:
a)SRAM based technology.
b)Segmented connection between elements.
c)Usually used for complex logic circuits.
d)Must be reprogrammed once the power is off.
e)Costly

CPLD:
a)Flash or EPROM based technology.
b)Continuous connection between elements.
c)Usually used for simpler or moderately complex logic circuits.
d)Need not be reprogrammed once the power is off.
e)Cheaper

11) What are dcm's?why they are used?

Digital clock manager (DCM) is a fully digital control system that
uses feedback to maintain clock signal characteristics with a
high degree of precision despite normal variations in operating
temperature and voltage.
That is clock output of DCM is stable over wide range of temperature and voltage , and also skew associated with DCM is minimal and all phases of input clock can be obtained . The output of DCM coming form global buffer can handle more load.


12) FPGA design flow?

13)what is slice,clb,lut?

I am taking example of xc3s500 to answer this question

The Configurable Logic Blocks (CLBs) constitute the main logic resource for implementing synchronous as well as combinatorial circuits.
CLB are configurable logic blocks and can be configured to combo,ram or rom depending on coding style
CLB consist of 4 slices and each slice consist of two 4-input LUT (look up table) F-LUT and G-LUT.

14) Can a clb configured as ram?

YES.

The memory assignment is a clocked behavioral assignment, Reads from the memory are asynchronous, And all the address lines are shared by the read and write statements.

15)What is purpose of a constraint file what is its extension?

The UCF file is an ASCII file specifying constraints on the logical design. You create this file and enter your constraints in the file with a text editor. You can also use the Xilinx Constraints Editor to create constraints within a UCF(extention) file. These constraints affect how the logical design is implemented in the target device. You can use the file to override constraints specified during design entry.

16) What is FPGA you are currently using and some of main reasons for choosing it?

17) Draw a rough diagram of how clock is routed through out FPGA?



18) How many global buffers are there in your current fpga,what is their significance?

There are 8 of them in xc3s5000
An external clock source enters the FPGA using a Global Clock Input Buffer (IBUFG), which directly accesses the global clock network or an Input Buffer (IBUF). Clock signals within the FPGA drive a global clock net using a Global Clock Multiplexer Buffer (BUFGMUX). The global clock net connects directly to the CLKIN input.

19) What is frequency of operation and equivalent gate count of u r project?

20)Tell me some of timing constraints you have used?

21)Why is map-timing option used?

Timing-driven packing and placement is recommended to improve design performance, timing, and packing for highly utilized designs.

22)What are different types of timing verifications?

Dynamic timing:
a. The design is simulated in full timing mode.
b. Not all possibilities tested as it is dependent on the input test vectors.
c. Simulations in full timing mode are slow and require a lot of memory.
d. Best method to check asynchronous interfaces or interfaces between different timing domains.
Static timing:
a. The delays over all paths are added up.
b. All possibilities, including false paths, verified without the need for test vectors.
c. Much faster than simulations, hours as opposed to days.
d. Not good with asynchronous interfaces or interfaces between different timing domains.

23) Compare PLL & DLL ?

PLL:
PLLs have disadvantages that make their use in high-speed designs problematic, particularly when both high performance and high reliability are required.
The PLL voltage-controlled oscillator (VCO) is the greatest source of problems. Variations in temperature, supply voltage, and manufacturing process affect the stability and operating performance of PLLs.

DLLs, however, are immune to these problems. A DLL in its simplest form inserts a variable delay line between the external clock and the internal clock. The clock tree distributes the clock to all registers and then back to the feedback pin of the DLL.
The control circuit of the DLL adjusts the delays so that the rising edges of the feedback clock align with the input clock. Once the edges of the clocks are aligned, the DLL is locked, and both the input buffer delay and the clock skew are reduced to zero.
Advantages:
· precision
· stability
· power management
· noise sensitivity
· jitter performance.


24) Given two ASICs. one has setup violation and the other has hold violation. how can they be made to work together without modifying the design?

Slow the clock down on the one with setup violations..
And add redundant logic in the path where you have hold violations.

25)Suggest some ways to increase clock frequency?

· Check critical path and optimize it.
· Add more timing constraints (over constrain).
· pipeline the architecture to the max possible extent keeping in mind latency req's.

26)What is the purpose of DRC?

DRC is used to check whether the particular schematic and corresponding layout(especially the mask sets involved) cater to a pre-defined rule set depending on the technology used to design. They are parameters set aside by the concerned semiconductor manufacturer with respect to how the masks should be placed , connected , routed keeping in mind that variations in the fab process does not effect normal functionality. It usually denotes the minimum allowable configuration.

27)What is LVs and why do we do that. What is the difference between LVS and DRC?

The layout must be drawn according to certain strict design rules. DRC helps in layout of the designs by checking if the layout is abide by those rules.
After the layout is complete we extract the netlist. LVS compares the netlist extracted from the layout with the schematic to ensure that the layout is an identical match to the cell schematic.

28)What is DFT ?

DFT means design for testability. 'Design for Test or Testability' - a methodology that ensures a design works properly after manufacturing, which later facilitates the failure analysis and false product/piece detection
Other than the functional logic,you need to add some DFT logic in your design.This will help you in testing the chip for manufacturing defects after it come from fab. Scan,MBIST,LBIST,IDDQ testing etc are all part of this. (this is a hot field and with lots of opportunities)

29) There are two major FPGA companies: Xilinx and Altera. Xilinx tends to promote its hard processor cores and Altera tends to promote its soft processor cores. What is the difference between a hard processor core and a soft processor core?

A hard processor core is a pre-designed block that is embedded onto the device. In the Xilinx Virtex II-Pro, some of the logic blocks have been removed, and the space that was used for these logic blocks is used to implement a processor. The Altera Nios, on the other hand, is a design that can be compiled to the normal FPGA logic.

30)What is the significance of contamination delay in sequential circuit timing?


31)When are DFT and Formal verification used?

DFT:
· manufacturing defects like stuck at "0" or "1".
· test for set of rules followed during the initial design stage.

Formal verification:
· Verification of the operation of the design, i.e, to see if the design follows spec.
· gate netlist == RTL ?
· using mathematics and statistical analysis to check for equivalence.

32)What is Synthesis?

Synthesis is the stage in the design flow which is concerned with translating your Verilog code into gates - and that's putting it very simply! First of all, the Verilog must be written in a particular way for the synthesis tool that you are using. Of course, a synthesis tool doesn't actually produce gates - it will output a netlist of the design that you have synthesised that represents the chip which can be fabricated through an ASIC or FPGA vendor.

33)We need to sample an input or output something at different rates, but I need to vary the rate? What's a clean way to do this?

Many, many problems have this sort of variable rate requirement, yet we are usually constrained with a constant clock frequency. One trick is to implement a digital NCO (Numerically Controlled Oscillator). An NCO is actually very simple and, while it is most naturally understood as hardware, it also can be constructed in software. The NCO, quite simply, is an accumulator where you keep adding a fixed value on every clock (e.g. at a constant clock frequency). When the NCO "wraps", you sample your input or do your action. By adjusting the value added to the accumulator each clock, you finely tune the AVERAGE frequency of that wrap event. Now - you may have realized that the wrapping event may have lots of jitter on it. True, but you may use the wrap to increment yet another counter where each additional Divide-by-2 bit reduces this jitter. The DDS is a related technique. I have two examples showing both an NCOs and a DDS in my File Archive. This is tricky to grasp at first, but tremendously powerful once you have it in your bag of tricks. NCOs also relate to digital PLLs, Timing Recovery, TDMA and other "variable rate" phenomena.

VHDL Interview Questions

What is the difference between using direct instntiations and component ones except that you need to declare the component ?

What is the use of BLOCKS ?

What is the use of PROCEDURES?

What is the usage of using more then one architecture in an entity?

What is a D-latch? Write the VHDL Code for it?

Implement D flip-flop with a couple of latches? Write a VHDL Code for a D flip-flop?

Differences between Signals and Variables in VHDL? If the same code is written using Signals and Variables what does it synthesize to?

Differences between functions and Procedures in VHDL?

Explain the concept of a Clock Divider Circuit? Write a VHDL code for the same?

What you would use in RTL a 'boolean' type or a 'std_logic' type and why.

What are/may be the implications of using an 'integer' type in RTL.

A timing path fails: what are your options?

What are VHDL structures, give an example to exploit them

What is grey coding, any example where they are used

Discuss Async interfaces

Metastability

Synopsys unwanted latch

Verilog blocking vs non-blocking

VHDL variables: example where you have to use them

What is pipelining and how it may improve the performance

What are multicycle paths.

What are false paths

What are Async counters, what are advantages of using these over sync counters. and what are the disadvantages

Sensitivity List:
How does it matter.What will happen
if you dont include a signal in the sensitivity list
and use/read it inside the process

How you will implement a C language pointer in VHDL

What is Design For Test and why it is done.

What is clock gating? How and why it is done.
Low Power: discuss how it may be done

Discuss disadvantages/challenges of shrinking technology

What is pipelining, how may it affect the performance of a design
What is the difference between transport delays and inertial delays in VHDL
What determines the max frequency a digital design may work on
Why thold(hold time) is not included in the calculation for the above.
What will happen if output of an inverter is shorted to its input
What is noise margin.
Why are p-mos larger than n-mos in CMOS design.
Draw DC curve of inverter and Re-Draw it if pmos and nmos are equal.
What is Latch-up
How can an Inverter work as an amplifier
Design a state machine which divides the input frequency of a clock by 3.

Why does a pass gate requires two transistors(1 N and 1 P type) Can we use a
single transistor N or P type in a pass gate? If not why? and if yes then in what conditions?

Why CMOS why not N-MOS or P-MOS logic, when we know that the number
of gates required in CMOS are grater than in n-mos or p-mos logic.

How much is the max fan out of a typical CMOS gate. Or alternatively,

discuss the limiting factors.

What are dynamic logic gates? What are their advantages over conventional logic gates

Design a digital circuit to delay the negative edge of the input signal by 2 clock cycles

What is the relation between binary encoding and grey(or gray) encoding.

Write a vhdl function to implement a length independent grey code counter.
alternatively, discuss the logic to do that.

How you will constraint a combinational logic path through your design
in dc_shell.

Make a T Flip Flop using a D Flip Flop

How you will make a Nand Gate function like an inverter.

Design a state machine to detect a '1101' pattern in a stream.
Detect both, overlapping and non overlapping patterns.

What are MISRs, example usage?

Verilog Interview Questions

1. What is the difference between Behavior modeling and RTL modeling?
2. What is the benefit of using Behavior modeling style over RTL modeling?
3. What is the difference between blocking assignments and non-blocking assignments ?
4. How do you implement the bi-directional ports in Verilog HDL
5. How to model inertial and transport delay using Verilog?
6. How to synchronize control signals and data between two different clock domains?
7. Create 4 bit multiplier using a ROM and what will be the size of the ROM. How can you realize it when the outputs are specified.
8. How can you swap 2 integers a and b, without using a 3rd variable
9. Which one is preferred? 1's complement or 2's complement and why?
10. Which one is preferred in FSM design? Mealy or Moore? Why?
11. Which one is preferred in design entry? RTL coding or Schematic? Why?
12. Design a 2 input OR gate using a 2:1 mux.
13. Design a 2 input AND gate using a 2 input XOR gate.
14. Design a hardware to implement following equations without using multipliers or dividers.
a. out = 7x + 8y;
b. out = .78x + .17y;
15. Design Gray counter to count 6.
16. Design XOR gate using just NAND gates.
17. Create "AND" gate using a 2:1 multiplexer. (Create all other gates too.)
18. How are blocking and non-blocking statements executed?
19. How do you model a synchronous and asynchronous reset in Verilog?
20. What happens if there is connecting wires width mismatch?
21. What are different options that can be used with $display statement in Verilog?
22. Give the precedence order of the operators in Verilog.
23. Should we include all the inputs of a combinational circuit in the sensitivity list? Give reason.
24. Give 10 commonly used Verilog keywords.
25. Is it possible to optimize a Verilog code such that we can achieve low power design?
26. Which is updated first: signal or variable?

Basic Digital Interview Questions

What is the function of a D flip-flop, whose inverted output is connected to its input ?


Design a circuit to divide input frequency by 2.


Design a divide-by-3 sequential circuit with 50% duty cycle.


Design a divide-by-5 sequential circuit with 50% duty cycle.


What are the different types of adder implementations ?


Draw a Transmission Gate-based D-Latch.


Give the truth table for a Half Adder. Give a gate level implementation of it.

Design an XOR gate from 2:1 MUX and a NOT gate


What is the difference between a LATCH and a FLIP-FLOP ?


* Latch is a level sensitive device while flip-flop is an edge sensitive device.
* Latch is sensitive to glitches on enable pin, whereas flip-flop is immune to glitches.
* Latches take less gates (also less power) to implement than flip-flops.
* Latches are faster than flip-flops.

Design a D Flip-Flop from two latches.

Design a 2 bit counter using D Flip-Flop.

What are the two types of delays in any digital system ?

Design a Transparent Latch using a 2:1 Mux.

Design a 4:1 Mux using 2:1 Muxes and some combo logic.

What is metastable state ? How does it occur ?


What is metastability ?


Design a 3:8 decoder


Design a FSM to detect sequence "101" in input sequence.


Convert NAND gate into Inverter, in two different ways.


Design a D and T flip flop using 2:1 mux; use of other components not allowed, just the mux.


Design a divide by two counter using D-Latch.


Design D Latch from SR flip-flop.


Define Clock Skew , Negative Clock Skew, Positive Clock Skew.


What is Race Condition ?


Design a 4 bit Gray Counter.


Design 4-bit Synchronous counter, Asynchronous counter.


Design a 16 byte Asynchronous FIFO.


What is the difference between an EEPROM and a FLASH ?


What is the difference between a NAND-based Flash and a NOR-based Flash ?


You are given a 100 MHz clock. Design a 33.3 MHz clock with and without 50&37; duty cycle.


Design a Read on Reset System ?


Which one is superior: Asynchronous Reset or Synchronous Reset ? Explain.


Design a State machine for Traffic Control at a Four point Junction.


What are FIFO's? Can you draw the block diagram of FIFO? Could you modify it to make it asynchronous FIFO ?


How can you generate random sequences in digital circuits?

Digital Design Interview Questions

Q. Design a logic which mimics a infinite width register. It takes input serially 1 bit at a time.
Output is asserted high when this register holds a value which is divisible by 5.
For example as in Figure 1.

Q.Design a block which has 3 inputs as followed.
1. system clock of pretty high freq
2. asynch clock input P
3. asynch clock input Q
P and Q clocks have 50% duty cycle each. Their frequencies are close enough and they have
phase difference. Design the block to generate these outputs.
1. PeqQ : goes high if periods of P and Q are same
2. PleQ : goes high if P’s period is less than that of Q.
3. PgrQ : goes high if P’s period is greater than that of Q.


Q. What’s the difference between a latch and a flip-flop? Write Verilog RTL code for each. (This is
one of the most common questions but still some EE’s don’t know how to explain it correctly!)

Q. Design a black box whose input clock and output relationship as shown in Figure 2.

Q. Design a digital circuit to delay the negative edge of the input
signal by 2 clock cycles as shown in Figure 3.

Q. Design a Pattern matching block
- Output is asserted if pattern "101" is detected in last 4 inputs.
- How will you modify this design if it is required to detect same "101" pattern anywhere in last
8 samples?

Q. The digital circuit is shown in Figure 4 with logic delay (dly3) and two clock buffer delays (dly1,
dly2).
- How will you fix setup timing violations occurring at pin B?
- How will you fix hold violations occurring at pin B?
(Hint: Change the values of three delays to get desired effect)

Q. As shown in Figure 5 Sender sends data at the rate of 80 words / 100 clocks
Receiver can consume at the rate of 8 words / 10 clocks
Calculate the depth of FIFO so that no data is dropped.
Assumptions: There is no feedback or handshake mechanism. Occurrence of data in that
time period is guaranteed but exact place in those clock cycles is indeterminate.

Q. Optical sensors A and B are positioned at 90 degrees to each other as shown in Figure 6.
Half od the disc is white and remaining is black. When black portion is under sensor it
generates logic 0 and logic 1 when white portion is under sensor.
Design Direction finder block using digital components (flip flops and gates) to indicate
speed. Logic 0 for clockwise and Logic 1 for counter clockwise.

Q. Will the design in Figure 7 work satisfactorily?
Assumptions: thold = tsetup = tclock_out = tclock_skew = 1ns.
After reset A = 0, B = 1

Q. Design a 4:1 mux in Verilog as in Figure 8.
· Multiple styles of coding. e.g.
Using if-else statements
if(sel_1 == 0 && sel_0 == 0) output = I0;
else if(sel_1 == 0 && sel_0 == 1) output = I1;
else if(sel_1 == 1 && sel_0 == 0) output = I2;
else if(sel_1 == 1 && sel_0 == 1) output = I3;
Using case statement
case ({sel_1, sel_0})
00 : output = I0;
01 : output = I1;
10 : output = I2;
11 : output = I3;
default : output = I0;
endcase
· What are the advantages / disadvantages of each coding style shown above?
· How Synthesis tool will give result for above codes?
· What happens if default statement is removed in case statement?
· What happens if combination 11 and default statement is removed? (Hint Latch
inference)
(Comments : Though this questions looks simple and out of text books, the answers to
supporting questions can come only after some experience / experimentation.)

Q. Design a FSM (Finite State Machine) to detect a sequence 10110 as shown in Figure 9.
· Have a good approach to solve the design problem.
· Know the difference between Mealy, Moore, 1-Hot type of state encoding.
· Each state should have output transitions for all combinations of inputs.
· All states make transition to appropriate states and not to default if sequence is broken.
e.g. S3 makes transition to S2 in example shown.
· Take help of FSM block diagram to write Verilog code.

Q. One more sequence detector as in Figure 10:
Design a FSM (Finite State Machine) to detect more than one "1"s in last 3 samples.
For example: If the input sampled at clock edges is 0 1 0 1 0 1 1 0 0 1
then output should be 0 0 0 1 0 1 1 1 0 0 as shown in timing diagram.
And yes, you have to design this FSM using not more than 4 states!!

Q. Design a state machine to divide the clock by 3/2 as shown in Figure 11.
(Hint: 2 FSMs working on posedge and negedge)

Q. Draw timing diagrams for circuit in Figure 12.

Q. For Figure 13 waveforms,
· What is the maximum frequency at which this circuit can operate?
· What is the minimum width of input pulse and position?
· Problem can be given interesting twist by specifying all delays in min and max types.

Q. Design a Digital Peak Detector in Verilog as in Figure 14.

Q. Design a RZ (return to zero )circuit. Design a clock to pulse circuit in Verilog / hardware gates as in Figure 15.

Q: how to design a divide-by-3 counter with equal duty cycle ?
Here is one of the solutions...as shown in Figure 16.
Start with the timing diagram. It shows an input clock, an output of a regular divide-by-3
counter and an output of divide-by-3 counter with 50% duty cycle.

It is obvious from the diagram, that we have to use both rising and falling edges of the
input clock.
The next drawing is a state diagram as in Figure 17.
On this diagram R - is a rising edge of input clock, and F - is a falling edge.
How many FF do we need to implement 6 states? At least 3. In this example I am going
to use 4 D-type FF just to simplify the design.
Now, look at the Figure 18. Q0 ... Q3 are the outputs of FFs. Q - is the output of the
devider with 50% duty cycle. In the first raw the outputs are in the initial state: 0000. In
the second raw - the data after the first rising edge and so on.The status of the FFs’ ouputs
is changing on every rising or falling edge of the input clock according to the information
on D-inputs. So, D-inputs should have the data before the clock edge.

These equations are resulting from the table analysis:
D1 = Q0
D2 = Q1
D3 = Q2
D0 = (Q1+Q2+Q3)’
Q = Q0*Q1’*Q2’*Q3’+Q0*Q1*Q2’*Q3’+Q0’*Q1*Q2*Q3’ =
Q1*Q3’(Q0*Q2’+Q0’*Q2)+Q0*Q1’*Q2’*Q3’
'The circuit diagram is shown in Figure 19.