Digital Design Interview Questions

Q. Design a logic which mimics a infinite width register. It takes input serially 1 bit at a time.
Output is asserted high when this register holds a value which is divisible by 5.
For example as in Figure 1.

Q.Design a block which has 3 inputs as followed.
1. system clock of pretty high freq
2. asynch clock input P
3. asynch clock input Q
P and Q clocks have 50% duty cycle each. Their frequencies are close enough and they have
phase difference. Design the block to generate these outputs.
1. PeqQ : goes high if periods of P and Q are same
2. PleQ : goes high if P’s period is less than that of Q.
3. PgrQ : goes high if P’s period is greater than that of Q.


Q. What’s the difference between a latch and a flip-flop? Write Verilog RTL code for each. (This is
one of the most common questions but still some EE’s don’t know how to explain it correctly!)

Q. Design a black box whose input clock and output relationship as shown in Figure 2.

Q. Design a digital circuit to delay the negative edge of the input
signal by 2 clock cycles as shown in Figure 3.

Q. Design a Pattern matching block
- Output is asserted if pattern "101" is detected in last 4 inputs.
- How will you modify this design if it is required to detect same "101" pattern anywhere in last
8 samples?

Q. The digital circuit is shown in Figure 4 with logic delay (dly3) and two clock buffer delays (dly1,
dly2).
- How will you fix setup timing violations occurring at pin B?
- How will you fix hold violations occurring at pin B?
(Hint: Change the values of three delays to get desired effect)

Q. As shown in Figure 5 Sender sends data at the rate of 80 words / 100 clocks
Receiver can consume at the rate of 8 words / 10 clocks
Calculate the depth of FIFO so that no data is dropped.
Assumptions: There is no feedback or handshake mechanism. Occurrence of data in that
time period is guaranteed but exact place in those clock cycles is indeterminate.

Q. Optical sensors A and B are positioned at 90 degrees to each other as shown in Figure 6.
Half od the disc is white and remaining is black. When black portion is under sensor it
generates logic 0 and logic 1 when white portion is under sensor.
Design Direction finder block using digital components (flip flops and gates) to indicate
speed. Logic 0 for clockwise and Logic 1 for counter clockwise.

Q. Will the design in Figure 7 work satisfactorily?
Assumptions: thold = tsetup = tclock_out = tclock_skew = 1ns.
After reset A = 0, B = 1

Q. Design a 4:1 mux in Verilog as in Figure 8.
· Multiple styles of coding. e.g.
Using if-else statements
if(sel_1 == 0 && sel_0 == 0) output = I0;
else if(sel_1 == 0 && sel_0 == 1) output = I1;
else if(sel_1 == 1 && sel_0 == 0) output = I2;
else if(sel_1 == 1 && sel_0 == 1) output = I3;
Using case statement
case ({sel_1, sel_0})
00 : output = I0;
01 : output = I1;
10 : output = I2;
11 : output = I3;
default : output = I0;
endcase
· What are the advantages / disadvantages of each coding style shown above?
· How Synthesis tool will give result for above codes?
· What happens if default statement is removed in case statement?
· What happens if combination 11 and default statement is removed? (Hint Latch
inference)
(Comments : Though this questions looks simple and out of text books, the answers to
supporting questions can come only after some experience / experimentation.)

Q. Design a FSM (Finite State Machine) to detect a sequence 10110 as shown in Figure 9.
· Have a good approach to solve the design problem.
· Know the difference between Mealy, Moore, 1-Hot type of state encoding.
· Each state should have output transitions for all combinations of inputs.
· All states make transition to appropriate states and not to default if sequence is broken.
e.g. S3 makes transition to S2 in example shown.
· Take help of FSM block diagram to write Verilog code.

Q. One more sequence detector as in Figure 10:
Design a FSM (Finite State Machine) to detect more than one "1"s in last 3 samples.
For example: If the input sampled at clock edges is 0 1 0 1 0 1 1 0 0 1
then output should be 0 0 0 1 0 1 1 1 0 0 as shown in timing diagram.
And yes, you have to design this FSM using not more than 4 states!!

Q. Design a state machine to divide the clock by 3/2 as shown in Figure 11.
(Hint: 2 FSMs working on posedge and negedge)

Q. Draw timing diagrams for circuit in Figure 12.

Q. For Figure 13 waveforms,
· What is the maximum frequency at which this circuit can operate?
· What is the minimum width of input pulse and position?
· Problem can be given interesting twist by specifying all delays in min and max types.

Q. Design a Digital Peak Detector in Verilog as in Figure 14.

Q. Design a RZ (return to zero )circuit. Design a clock to pulse circuit in Verilog / hardware gates as in Figure 15.

Q: how to design a divide-by-3 counter with equal duty cycle ?
Here is one of the solutions...as shown in Figure 16.
Start with the timing diagram. It shows an input clock, an output of a regular divide-by-3
counter and an output of divide-by-3 counter with 50% duty cycle.

It is obvious from the diagram, that we have to use both rising and falling edges of the
input clock.
The next drawing is a state diagram as in Figure 17.
On this diagram R - is a rising edge of input clock, and F - is a falling edge.
How many FF do we need to implement 6 states? At least 3. In this example I am going
to use 4 D-type FF just to simplify the design.
Now, look at the Figure 18. Q0 ... Q3 are the outputs of FFs. Q - is the output of the
devider with 50% duty cycle. In the first raw the outputs are in the initial state: 0000. In
the second raw - the data after the first rising edge and so on.The status of the FFs’ ouputs
is changing on every rising or falling edge of the input clock according to the information
on D-inputs. So, D-inputs should have the data before the clock edge.

These equations are resulting from the table analysis:
D1 = Q0
D2 = Q1
D3 = Q2
D0 = (Q1+Q2+Q3)’
Q = Q0*Q1’*Q2’*Q3’+Q0*Q1*Q2’*Q3’+Q0’*Q1*Q2*Q3’ =
Q1*Q3’(Q0*Q2’+Q0’*Q2)+Q0*Q1’*Q2’*Q3’
'The circuit diagram is shown in Figure 19.

ASIC Interview Questions

An application-specific integrated circuit (ASIC) is an IC that is customized for a particular use or application, such as a chip which is designed to run a cellular handset.

1) Explain why & how a MOSFET works
2) Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes (a) with
increasing Vgs (b) with increasing transistor width (c) considering Channel Length
Modulation
3) Explain the various MOSFET Capacitances & their significance
4) Draw a CMOS Inverter. Explain its transfer characteristics
5) Explain sizing of the inverter
6)How do you size NMOS and PMOS transistors to increase the threshold voltage?
7) What is Noise Margin? Explain the procedure to determine Noise Margin
8) Give the expression for CMOS switching power dissipation
9) What is Body Effect?
10) Describe the various effects of scaling
11) Give the expression for calculating Delay in CMOS circuit
12) What happens to delay if you increase load capacitance?
13) What happens to delay if we include a resistance at the output of a CMOS circuit?
14) What are the limitations in increasing the power supply to reduce delay?
15) How does Resistance of the metal lines vary with increasing thickness and increasing
length?
16) You have three adjacent parallel metal lines. Two out of phase signals pass through
the outer two metal lines. Draw the waveforms in the center metal line due to
interference. Now, draw the signals if the signals in outer metal lines are in phase with
each other
17) What happens if we increase the number of contacts or via from one metal layer to
the next?
18) Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth
(b) for equal rise and fall times
19) Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate
later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one
would you place near the output?
20) Draw the stick diagram of a NOR gate. Optimize it
21) For CMOS logic, give the various techniques you know to minimize power
consumption
22) What is Charge Sharing? Explain the Charge Sharing problem while sampling data
from a Bus
23) Why do we gradually increase the size of inverters in buffer design? Why not give
the output of a circuit to one large inverter?
24) In the design of a large inverter, why do we prefer to connect small transistors in
parallel (thus increasing effective width) rather than lay out one transistor with large
width?
25) Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and
a 2 input Multiplexer. You can expect any simple 2 or 3 input gates)
26) Give the logic expression for an AOI gate. Draw its transistor level equivalent. Draw
its stick diagram
27) Why don’t we use just one NMOS or PMOS transistor as a transmission gate?
28) For a NMOS transistor acting as a pass transistor, say the gate is connected to VDD,
give the output for a square pulse input going from 0 to VDD
29) Draw a 6-T SRAM Cell and explain the Read and Write operations
30) Draw the Differential Sense Amplifier and explain its working. Any idea how to size
this circuit? (Consider Channel Length Modulation)
31) What happens if we use an Inverter instead of the Differential Sense Amplifier?
32) Draw the SRAM Write Circuitry
33) Approximately, what were the sizes of your transistors in the SRAM cell? How did
you arrive at those sizes?
34) How does the size of PMOS Pull Up transistors (for bit & bit- lines) affect SRAM’s
performance?
35) What’s the critical path in a SRAM?
36) Draw the timing diagram for a SRAM Read. What happens if we delay the enabling
of Clock signal?
37) Give a big picture of the entire SRAM Layout showing your placements of SRAM
Cells, Row Decoders, Column Decoders, Read Circuit, Write Circuit and Buffers
38) In a SRAM layout, which metal layers would you prefer for Word Lines and Bit
Lines? Why?
39) How can you model a SRAM at RTL Level?
40) What’s the difference between Testing & Verification?
41) For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0
and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some
redundant logic)
42) What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do
you avoid Latch Up?

Digital Design:

1) Give two ways of converting a two input NAND gate to an inverter
2) Given a circuit, draw its exact timing response. (I was given a Pseudo Random Signal
Generator; you can expect any sequential ckt)
3) What are set up time & hold time constraints? What do they signify? Which one is
critical for estimating maximum clock frequency of a circuit?
4) Give a circuit to divide frequency of clock cycle by two
5) Design a divide-by-3 sequential circuit with 50% duty circle. (Hint: Double the Clock)
6) Suppose you have a combinational circuit between two registers driven by a clock.
What will you do if the delay of the combinational circuit is greater than your clock
signal? (You can’t resize the combinational circuit transistors)
7) The answer to the above question is breaking the combinational circuit and pipelining
it. What will be affected if you do this?
8) What are the different Adder circuits you studied?
9) Give the truth table for a Half Adder. Give a gate level implementation of the same.
10) Draw a Transmission Gate-based D-Latch.
11) Design a Transmission Gate based XOR. Now, how do you convert it to XNOR?
(Without inverting the output)
12) How do you detect if two 8-bit signals are same?
13) How do you detect a sequence of "1101" arriving serially from a signal line?
14) Design any FSM in VHDL or Verilog.

Computer Architecture:

1) What is pipelining?
2) What are the five stages in a DLX pipeline?
3) For a pipeline with 'n' stages, what’s the ideal throughput? What prevents us from
achieving this ideal throughput?
4) What are the different hazards? How do you avoid them?
5) Instead of just 5-8 pipe stages why not have, say, a pipeline with 50 pipe stages?
6) What are Branch Prediction and Branch Target Buffers?
7) How do you handle precise exceptions or interrupts?
8) What is a cache?
9) What's the difference between Write-Through and Write-Back Caches? Explain
advantages and disadvantages of each.
10) Cache Size is 64KB, Block size is 32B and the cache is Two-Way Set Associative.
For a 32-bit physical address, give the division between Block Offset, Index and Tag.
11) What is Virtual Memory?
12) What is Cache Coherency?
13) What is MESI?
14) What is a Snooping cache?
15) What are the components in a Microprocessor?
16) What is ACBF(Hex) divided by 16?
17) Convert 65(Hex) to Binary
18) Convert a number to its two's compliment and back
19) The CPU is busy but you want to stop and do some other task. How do you do it?

Some More Questions:

1. What is t he dif f er ence bet ween a lat ch and a f lip f lop. For t he same input ,
how
would t he out put look f or a lat ch and f or a f lip-f lop.
2. Finit e st at e machines:
(2.1)Design a st at e-machine (or dr aw a st at e-diagr am) t o give an out put ’ 1’
when t he # of A’ s ar e even
and # of B’ s ar e odd. The input is in t he f orm of a ser ial-st r eam (one-bit
per clock cycle). The input s could be of t he t ype A, B or C. At any given
clock cycle, t he out put is a ’ 1’ , pr ovided t he # of A’ s ar e even and # of B’ s
ar e odd. At any given clock cycle, t he out put is a ’ 0’ , if t he above condit ion
is not sat isf ied.
(2.2). To det ect t he sequence "abca" when t he input s can be a b c d.
3. minimize a boolean expr ession.
4. Dr aw t r ansist or level nand gat e.
5. Dr aw t he cr oss-sect ion of a CMOS inver t er .
6. Der iving t he vect or s f or t he st uck at 0 and st uck at 1 f ault s.
7. Given a boolean expr ession he asked me t o implement j ust wit h
muxes but not hing else.
8. Dr aw I d Vds cur ves f or mosf et s and explain dif f er ent r egions.
9. Given t he t r ansf er char act er ist ics of a black box dr aw t he
cir cuit f or t he black box.
10. Given a cir cuit and it s input s dr aw t he out put s exact t o t he t iming.
11. Given an inver t er wit h a par t icular t iming der ive an inver t er
using t he pr evious one but wit h t he r equir ed t iming ot her t han t he
pr evious one.
12. Change t he r ise t ime and f all t ime of a given cir cuit by not
changing t he t r ansist or sizes but by using cur r ent mir r or s.
13. Some pr oblems on clamping diodes.

Computer Architecture Quest ions:

1. Explain what is DMA?
2. what is pipelining?
3. what ar e super scalar machines and vliw machines?
4. what is cache?
5. what is cache coher ency and how is it eliminat ed?
6. what is wr it e back and wr it e t hr ough caches?
7. what ar e dif f er ent pipelining hazar ds and how ar e t hey eliminat ed.
8. what ar e dif f er ent st ages of a pipe?
9. eplain mor e about br anch pr edict ion in cont r olling t he cont r ol hazar ds
10. Give examples of dat a hazar ds wit h pseudo codes.
11. Caluculat ing t he number of set s given it s way and size in a cache?
12. How is a block f ound in a cache?
13. scor eboar d analysis.
14. What is miss penalt y and give your own ideas t o eliminat e it .
15. How do you impr ove t he cache per ormance.
16. Dif f er ent addr essing modes.
17. Comput er arithmet ic wit h t wo’ s complement s.
18. About har dwar e and software interrupt s.
19. What is bus content ion and how do you eliminat e it .
20. What is aliasing?
21) What is t he dif f er ence bet ween a lat ch and a f lip f lop?
22) What is t he r ace ar ound condit ion? How can it be over come?
23) What is t he pur pose of cache? How is it used?
24) What ar e t he t ypes of memory management ?